Advances in the field of semiconductor integrated circuits have brought about higher levels of integration. Accordingly, semiconductor manufacturing process advancements are driving the corresponding geometric dimensions of semiconductor devices to decreasingly smaller values. 10 micrometer (μm) gate lengths, for example, were common in the 1970's, but continuously advancing semiconductor manufacturing processes have reduced gate lengths to well below 100 nanometer (nm).
Continuing efforts to achieve higher levels of integration have also led to reductions in the separation distance between adjacent semiconductor features. For example, nanometer processes producing 65 nm and 45 nm gate lengths require a device spacing of, e.g., 120 nm to achieve reasonable yields within specified process margins.
In order to define the nanometer features and associated device spacing on a semiconductor substrate, geometric patterns defining such features must first be superimposed upon the semiconductor substrate. Several layers of geometric patterns are often required, whereby each pattern is superimposed upon each previous pattern during semiconductor substrate development. The geometric patterns that are used to define the various layers on the semiconductor substrate are defined by a process known as microlithography.
Generally speaking, the microlithographic process consists of several steps, whereby various layers of a starting material are first developed. The starting material, for example, may initially consist of a silicon or germanium substrate having gate oxide and polycrystalline silicon (polysilicon) layers deposited thereon.
Next, a hard mask layer may be applied in order to improve certain microlithographic qualities and etch resistance of a photoresist layer that is subsequently applied on top of the hard mask layer. Using a hard mask layer below the photoresist layer, for example, allows a reduction in the thickness of the photoresist layer, which becomes increasingly important as features defined by the photoresist patterns fall below 100 nm.
Finally, a layer of photoresist material is deposited above the hard mask layer by spin coating a uniform layer of photoresist over the entire surface of the starting material. The photoresist layer may then be selectively exposed to geometrically defined patterns of radiation, such as ultraviolet (UV) light, whereby the exposed areas are defined by an exposure tool, photomask, and/or computer data. A bottom anti-reflective coating (BARC) may also be deposited between the hard mask layer and the photoresist layer, so as to minimize detrimental interference effects that are caused by the photoresist exposure process, such as photoresist line width variation.
After exposure, the photoresist is subjected to a development process that converts the latent image in the photoresist into the final image. An oxygen plasma trimming process may also be employed to remove quantities of unwanted photoresist that remain after the photoresist development process is complete. The final image serves as the mask in subsequent subtractive, e.g., etching, or additive, e.g., ion implantation, steps to selectively remove, or deposit, material from/to the starting material to produce certain device features in the nanometer range.
The nanometer processes targeted at producing 65 nm feature sizes typically require final images that exhibit feature sizes on the order of, e.g., 50 nm. Obtaining 50 nm feature sizes using conventional single exposure processes, however, is challenging. As such, an exposure and development process is first employed to generate oversized features, e.g., 80 nm, within the final image of the photoresist layer. An oxygen plasma trimming process, for example, is then employed, whereby the photoresist is trimmed, both horizontally and vertically, to reduce the photoresist features defined by the final image from 80 nm to 50 nm.
Through use of the photoresist trimming process, the sizes of certain critical feature patterns, such as transistor gate length, may be advantageously reduced. Unfortunately, the photoresist trimming process also produces an undesirable reduction in the sizes of other critical feature patterns, such as poly-to-contact enclosure patterns and field poly width, thereby increasing the poly-to-contact and field poly line resistance beyond acceptable process margins. Efforts continue, therefore, to identify photoresist exposure, development, and trimming processes that provide selective reduction in certain critical pattern dimensions, while suppressing reduction in other critical pattern dimensions.